Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control

Execution trace graph analysis of dataflow programs has been demonstrated to be an effective way for exploring and optimizing the design space of many core applications. In this work a novel transformation from the execution trace graph to an event driven linear system is proposed. It is also illust...

Full description

Saved in:
Bibliographic Details
Published inProceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing pp. 1 - 6
Main Authors Casale-Brunet, S., Bezati, E., Mattavelli, M., Canale, M., Janneck, J. W.
Format Conference Proceeding
LanguageEnglish
Published European Electronic Chips & Systems design Initiat 01.10.2014
Subjects
Online AccessGet full text

Cover

Loading…
Abstract Execution trace graph analysis of dataflow programs has been demonstrated to be an effective way for exploring and optimizing the design space of many core applications. In this work a novel transformation from the execution trace graph to an event driven linear system is proposed. It is also illustrated how the trace space of can be effectively reduced and well known system control techniques can be efficiently used in order to find close to optimal solutions. In particular, the problem of finding a bounded buffer size configuration is proposed and solved using a model predictive controller. Two design examples, a JPEG and an MPEG HEVC decoder have been used to demonstrate the effectiveness of the approach.
AbstractList Execution trace graph analysis of dataflow programs has been demonstrated to be an effective way for exploring and optimizing the design space of many core applications. In this work a novel transformation from the execution trace graph to an event driven linear system is proposed. It is also illustrated how the trace space of can be effectively reduced and well known system control techniques can be efficiently used in order to find close to optimal solutions. In particular, the problem of finding a bounded buffer size configuration is proposed and solved using a model predictive controller. Two design examples, a JPEG and an MPEG HEVC decoder have been used to demonstrate the effectiveness of the approach.
Author Casale-Brunet, S.
Mattavelli, M.
Canale, M.
Bezati, E.
Janneck, J. W.
Author_xml – sequence: 1
  givenname: S.
  surname: Casale-Brunet
  fullname: Casale-Brunet, S.
  organization: EPFL SCI-STI-MM, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
– sequence: 2
  givenname: E.
  surname: Bezati
  fullname: Bezati, E.
  organization: EPFL SCI-STI-MM, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
– sequence: 3
  givenname: M.
  surname: Mattavelli
  fullname: Mattavelli, M.
  organization: EPFL SCI-STI-MM, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
– sequence: 4
  givenname: M.
  surname: Canale
  fullname: Canale, M.
  organization: Dipt. di Autom. e Inf., Politec. di Torino, Turin, Italy
– sequence: 5
  givenname: J. W.
  surname: Janneck
  fullname: Janneck, J. W.
  organization: Dept. of Comput. Sci., Lund Univ., Lund, Sweden
BookMark eNotkM1OAjEYRWuiiYq8gG76AmB_pu3UHSoqCYkm6pqU9itUy5S0MyhrX9wxsrqLk3sW5xwdN6kBhC4pGVNK9PX95HX2MmaEVmNFqZCMH6GhVrpnjClNJD1Fw1I-CCFUS00UO0M_02-wXRtSg9tsLOBVNts1No2J-xIKTh470xof0xfe5tTTTbnBt6lrHDi87LyHjItdg-tiaFb90WEHxsVkP3EGm3aQ97grf2yTHMTeAi7YNuwA29S0OcULdOJNLDA87AC9P0zf7p5G8-fH2d1kPgqsqtoR40KC1Y5Lpomuna0EIzWrgTIquDB-KYS3FkAKVVGuoOaC-9rWaikNKMMH6OrfGwBgsc1hY_J-cUjFfwFg4WOi
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/DASIP.2014.7115623
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEL
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE/IET Electronic Library (IEL)
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 9791092279061
EndPage 6
ExternalDocumentID 7115623
Genre orig-research
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
IEGSK
IERZE
OCL
RIE
RIL
ID FETCH-LOGICAL-i244t-2356ec9d3629098dc4520828e121535afb55fccee6574137e8353f8c87b6ae7a3
IEDL.DBID RIE
IngestDate Thu Jun 29 18:37:59 EDT 2023
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i244t-2356ec9d3629098dc4520828e121535afb55fccee6574137e8353f8c87b6ae7a3
PageCount 6
ParticipantIDs ieee_primary_7115623
PublicationCentury 2000
PublicationDate 2014-Oct.
PublicationDateYYYYMMDD 2014-10-01
PublicationDate_xml – month: 10
  year: 2014
  text: 2014-Oct.
PublicationDecade 2010
PublicationTitle Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing
PublicationTitleAbbrev DASIP
PublicationYear 2014
Publisher European Electronic Chips & Systems design Initiat
Publisher_xml – name: European Electronic Chips & Systems design Initiat
SSID ssj0001969072
Score 1.6053554
Snippet Execution trace graph analysis of dataflow programs has been demonstrated to be an effective way for exploring and optimizing the design space of many core...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Algorithm design and analysis
Heuristic algorithms
Optimization
Petri nets
Predictive control
System recovery
Transform coding
Title Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
URI https://ieeexplore.ieee.org/document/7115623
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LT4NAEN60PenFR2t8Zw8ehVLYBdabjzbVpKaJNumtWfZhTE0xFeLj6h93BmirxoM3Qlhgl1m-md1vviHkxIukpyOBVCmY5CyQkSMS03G0tQkEJDbyi3SxwW3YH7GbMR_XyOkyF8YYU5DPjIuHxV6-TlWOS2XtCNwXgOs6qceeX-ZqrdZTBMZ5_iIvxhPtq_O76yGSt5hbNfxRQaUAkN4GGSweXfJGpm6eJa76-KXK-N932yStVaoeHS5BaIvUzGybrH9TGWySz-6bUYV90Wwu4fpCpJrKSo6EppYiT9Q-pa-0omu9nNELrLdkNE1yrKBCIQgGUMLcdWioqQbTABicUgyoYTa8UyTQP9CisA7cBbd_8EdKKyp8i4x63fvLvlPVXnAeAfAzxw94aJTQgG_CE7FWjPuodmdQjSLg0iacWwWdCzn4JEFkwJMLbKziKAmliWSwQxqzdGZ2CU38UIGj1lHcWHC-tAiYZL70YsGYZpLvkSYO5-S5lNeYVCO5__fpA7KGn7Tk0x2SRjbPzRH4BVlyXBjEF8_ouic
link.rule.ids 310,311,786,790,795,796,802,27958,55109
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LT8JAEN4gHtSLDzC-3YNHC6XdbbvefEBAgZAICTey3YcxGDBY4uPqH3emFFDjwVvTdNvudrbfzO433xBy5obS1aFAqhRMcubL0BGxqTja2hgCEht6abpYqx3Ue-y2z_s5cr7IhTHGpOQzU8LDdC9fj9UUl8rKIbgvANcrZBVw3hWzbK3liorASM-bZ8a4onxzed_oIH2LlbKmP2qopBBS2ySt-cNnzJFhaZrEJfXxS5fxv2-3RYrLZD3aWcDQNsmZ0Q7Z-KYzWCCf1TejUgujyUTC9alMNZWZIAkdW4pMUfs0fqUZYevlgl5hxSWjaTzFGioUwmCAJcxeh4aaajAOAMIhxZAa5sM7RQr9A01L68BdcAMIf6U0I8MXSa9W7V7Xnaz6gvMIkJ84ns8Do4QGhBOuiLRi3EO9O4N6FD6XNubcKuhcwMEr8UMDvpxvIxWFcSBNKP1dkh-NR2aP0NgLFLhqFcWNBfdLC59J5kk3EoxpJvk-KeBwDp5nAhuDbCQP_j59Stbq3VZz0Gy07w7JOn7eGbvuiOSTydQcg5eQxCepcXwByyO9fQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+the+2014+Conference+on+Design+and+Architectures+for+Signal+and+Image+Processing&rft.atitle=Execution+trace+graph+analysis+of+dataflow+programs%3A+Bounded+buffer+scheduling+and+deadlock+recovery+using+model+predictive+control&rft.au=Casale-Brunet%2C+S.&rft.au=Bezati%2C+E.&rft.au=Mattavelli%2C+M.&rft.au=Canale%2C+M.&rft.date=2014-10-01&rft.pub=European+Electronic+Chips+%26+Systems+design+Initiat&rft.spage=1&rft.epage=6&rft_id=info:doi/10.1109%2FDASIP.2014.7115623&rft.externalDocID=7115623