Discrete domain modeling of an all-digital frequency locked loop

• Published in: 2017 International Semiconductor Conference (CAS) pp. 247 - 250
• Main Authors: Szopos, Erwin, Saracut, Ioana, Kirei, Botond Sandor, Dana Topa, Marina
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2017
• Subjects: all-digital frequency locked loop; Frequency control; Frequency locked loops; Frequency measurement; Jitter; Oscillators; Phase locked loops; Signal resolution; Verilog behavioral description; Z-domain model
• DOI: 10.1109/SMICND.2017.8101214

In this paper an all-digital frequency locked loop - which is composed of a digitally controlled oscillator, a counter and a latch (with the scope of frequency detection) and an accumulator in the control loop - is modeled in the z-domain considering two significant error sources that occur in its structure: the finite resolution of the digital signals and the inaccuracy of the frequency detection. The developed discrete time model was implemented in LabVIEW and it was compared against a structural description of the frequency locked loop achieved in Verilog. Simulation results for digitally controlled oscillator with 8, 10 and 12 bits resolution were obtained for both models. Employing a low resolution digitally controlled oscillator the loop can achieve frequency lock in less time, but its jitter performance is worst. The jitter can be improved if higher resolution is used, at the cost of a higher frequency lock time. The peak-to-peak jitter performance was plotted against the resolution of the digitally controlled oscillator that is helpful to determine the minimum for a desiredjitter.