APA (7th ed.) Citation

Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2018, June). A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. 2018 IEEE Symposium on VLSI Circuits, 141-142. https://doi.org/10.1109/VLSIC.2018.8502421

Chicago Style (17th ed.) Citation

Valavi, Hossein, Peter J. Ramadge, Eric Nestler, and Naveen Verma. "A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement." 2018 IEEE Symposium on VLSI Circuits Jun. 2018: 141-142. https://doi.org/10.1109/VLSIC.2018.8502421.

MLA (9th ed.) Citation

Valavi, Hossein, et al. "A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement." 2018 IEEE Symposium on VLSI Circuits, Jun. 2018, pp. 141-142, https://doi.org/10.1109/VLSIC.2018.8502421.