Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node - Xue, Lin; Ching, Chi; Kontos, Alex; Ahn, Jaesoo; Wang, Xiaodong; Whig, Renu; Tseng, Hsin-wei; Howarth, James; Hassan, Sajjad; Chen, Hao; Bangar, Mangesh; Liang, Shurong; et al. (2018 IEEE Symposium on VLSI Technology, 2018)
This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm*µm 2 , H SAF ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10 −6 write error rate was reached at 0.4 pJ, V BD was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400°C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.