Strategies to cope with plasma charging damage in design and layout phases

• Published in: 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005 pp. 91 - 98
• Main Authors: Wang, Z., Ackaert, J., Scarpa, A., Salm, C., Kuper, F.G., Vugts, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Circuits; Metal-insulator structures; Plasma applications; Plasma devices; Plasma materials processing; Plasma measurements; Plasma sources; Plasma temperature; Protection; Semiconductor diodes
• DOI: 10.1109/ICICDT.2005.1502600
• ISBN: 9780780390812; 0780390814
• ISSN: 2381-3555

In this paper, strategics to cope with plasma charging damage in design and layout phases are discussed. A semi-empirical model is addressed first. With this model, a designer is able to predict the plasma charging induced yield loss of the circuit, if the antenna ratio (AR) distribution of the circuit is available. Then a novel first order self-balancing interconnect layout design is proposed to reduce the plasma charging damage. Moreover, the temperature effect on the protection diode is discussed and a strategic diode protection scheme for plasma charging damage is proposed. In addition to these general methods, a set of design rules is given to protect floating metal-insulator-metal (MIM) capacitors from plasma charging damage.