Architecture design of reconfigurable pipelined datapaths

• Published in: Proceedings 20th Anniversary Conference on Advanced Research in VLSI pp. 23 - 40
• Main Authors: Cronquist, D.C., Fisher, C., Figueroa, M., Franklin, P., Ebeling, C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Bridges; Computer applications; Computer architecture; Costs; High performance computing; Pipelines; Programmable control; Reconfigurable architectures; Scientific computing; Video signal processing
• ISBN: 0769500560; 9780769500560
• ISSN: 1522-869X; 2332-5801
• DOI: 10.1109/ARVLSI.1999.756035

This paper examines reconfigurable pipelined datapaths (RaPiDs), a new architecture style for computation-intensive applications that bridges the cost/performance gap between general purpose and application specific architectures. RaPiDs can provide significantly higher performance than general purpose processors on a wide range of applications from the areas of video and signal processing, scientific computing and communications. Moreover, RaPiDs provide the flexibility that does not come with application-specific architectures. A RaPiD architecture is optimized for highly repetitive, computationally-intensive tasks. Very deep application-specific computation pipelines can be configured that deliver very high performance for a wide range of applications. RaPiDs achieve this using a coarse-grained reconfigurable architecture that mixes the appropriate amount of static configuration with dynamic control. We describe the fundamental features of a RaPiD architecture, including the linear array of functional units, a programmable segmented bus structure, and a programmable control architecture. In addition, we outline the floorplan of the architecture and provide timing data for the most critical paths. We conclude with performance numbers for several applications on an instance of a RaPiD architecture.