Hessenberg Reduction with Transient Error Resilience on GPU-Based Hybrid Architectures

• Published in: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) pp. 653 - 662
• Main Authors: Yulu Jia, Luszczek, Piotr, Dongarra, Jack
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2016
• Subjects: Algorithm design and analysis; Central Processing Unit; Fault tolerance; Fault tolerant systems; GPGPU; Graphics processing units; Hessenberg reduction; similarity transformation; Transient analysis; Transistors
• DOI: 10.1109/IPDPSW.2016.34

Graphics Processing Units (GPUs) have been seeing widespread adoption in the field of scientific computing, owing to the performance gains provided on computation-intensive applications. In this paper, we present the design and implementation of a Hessenberg reduction algorithm immune to simultaneous soft-errors, capable of taking advantage of hybrid GPU-CPU platforms. These soft-errors are detected and corrected on the fly, preventing the propagation of the error to the rest of the data. Our design is at the intersection between several fault tolerant techniques and employs the algorithm-based fault tolerance technique, diskless checkpointing, and reverse computation to achieve its goal. By utilizing the idle time of the CPUs, and by overlapping both host-side and GPU-side workloads, we minimize the resilience overhead. Experimental results have validated our design decisions as our algorithm introduced less than 2% performance overhead compared to the optimized, but fault-prone, hybrid Hessenberg reduction.