Removing JTAG bottlenecks in system interconnect test

This work presents a new methodology that removes JTAG bottlenecks in system interconnect test. JTAG test has a limitation by targeting only low-speed testing. But, the system interconnect test requires the test to be run at system clock speed through the cluster of the network and also needs to dia...

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Bibliographic Details
Published in2004 International Conferce on Test pp. 173 - 180
Main Authors Hong-Shin Jun, Chung, S.S., Baeg, S.H.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2004
Washington DC International Test Conference
Subjects
Applied sciences
Circuit properties
Clocks
Delay
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Frequency synchronization
High speed optical techniques
Logic testing
Miscellaneous
Optical and optoelectronic circuits
Optical buffering
Optical interconnections
Optical receivers
Optical transmitters
System testing
Optical signal
Optical coupling
Delay time
High frequency
Clock
Synchronization
Optical interconnection
Interconnected system
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Summary:This work presents a new methodology that removes JTAG bottlenecks in system interconnect test. JTAG test has a limitation by targeting only low-speed testing. But, the system interconnect test requires the test to be run at system clock speed through the cluster of the network and also needs to diagnose the skew and delay characteristics of the cluster. Resolving the synchronization issue between a high-speed pattern clock and TCK, the proposed technique enables high frequency interconnection testing, cluster testing, and delay testing. Experimental results with test vehicles show that the test technique can be used with complex interconnections including differential signal lines, AC coupling, latency, and optical signal interconnections.
ISBN:0780385802
9780780385801
DOI:10.1109/TEST.2004.1386950