The New Topology of Multilevel Inverter with Reduced Number of Switches

• Published in: 2020 11th IEEE Control and System Graduate Research Colloquium (ICSGRC) pp. 94 - 99
• Main Authors: Jefry, Nur Atiqah, Kah Haw, Law, Ing, Wong Kiing
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2020
• Subjects: cascaded h-bridge multilevel inverter; diode clamped multilevel inverter
• DOI: 10.1109/ICSGRC49013.2020.9232502

In this paper, a new multilevel inverter topology is proposed. This novel topology utilizes the cascaded feature as well as the isolated DC sources presented in Cascaded H-bridge Multilevel inverter (CHB-MLI) and the clamping diode in Diode Clamped Multilevel Inverter (DC-MLI). With these merits combined, an inverter topology with 18 total component counts had being emerged. This proposed topology could produce up to 17 levels of output according the ratio assigned to its DC sources. Apart from producing greater number of output voltage level with considerably low number of component counts, this study also aims to meet the THD limit set by IEEE standard (i.e 5%) for all voltage application below 69kV. In order to verify the functionality of this proposed topology, it being simulated using Matlab/Simulink using different modulation index. The change in THD percentage, the number of voltage output and RMS voltage are being observed and thoroughly discussed. Lastly, a comparative study with recently presented topologies is also being conducted to analyze the novelty of the proposed topology.