A Parallel Algorithm and Scalable Architecture for Routing in Beneš Networks

• Published in: Annual Joint Conference of the IEEE Computer and Communications Societies pp. 921 - 930
• Main Authors: Zecharia, Rami, Shavitt, Yuval
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.05.2024
• Subjects: Beneš; Complexity theory; Computer architecture; Computers; Hardware; Network; Optical Switch; Optical switches; Routing; Switch Fabric; Wires
• ISSN: 2641-9874
• DOI: 10.1109/INFOCOM52122.2024.10621315

Beneš/CLOS architectures are common scalable interconnection networks widely used in backbone routers, data centers, on-chip networks, multi-processor systems, and parallel computers. Recent advances in Silicon Photonic technology, especially MZI technology, have made Beneš networks a very attractive scalable architecture for optical circuit switches.Numerous routing algorithms for Beneš networks were developed starting with linear algorithms having time complexity of O(N log 2 N) steps. Parallel routing algorithms were developed to satisfy the stringent timing requirements of high-performance switching networks and have time complexity of O((log 2 N) 2 ).However, their implementation requires O(N 2 log 2 N) wires (termed connectivity complexity), and thus are difficult to scale.We present a new routing algorithm for Beneš networks combined with a scalable hardware architecture that supports full and partial input permutations. The processing time of the algorithm is limited to O((log 2 N) 2 ) steps (iterations) by potentially forfeiting routing of a few input demands; however achieves close to 100% utilization for both full and partial input permutations. The algorithm and architecture allow a reduction of the connectivity complexity to O(N 2 ), a logN improvement over previous solutions.We prove the algorithm correctness, and analyze its performance analytically and with large scale simulations.