A Sub-Sampling Front-End with 12 fF Load for On-Chip Measurements - R., Aashish T.; Chatterjee, Shouri (Conference proceedings : Midwest Symposium on Circuits and Systems, 2024)
A sub-sampling front-end with a low capacitive loading followed by a second order ΣΔ ADC is presented. The front end is designed in the UMC 65nm low-power CMOS process and has a power consumption of 110 µW from a 1.2 V supply. The ADC has a simulated SQNR of around 74 dB and an ENOB of around 12 bits. The time constant of the sampling front-end comes to nearly 0.76 ps. The entire front end occupies an area of 200 µm x 550 µm.