Thermal budget optimization on Strained Silicon-On-Insulator (SSOI) CMOS

• Published in: 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) pp. 118 - 119
• Main Authors: Huang, R.M., Lin, Y.H., Tsai, S.H., Yang, C.W., Liu, E.C., Hsieh, Y.S., Cayrefourcq, I., Tsai, C.T., Ma, G.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2008
• Subjects: Annealing; Capacitive sensors; Implants; MOS devices; Silicon on insulator technology; Tensile strain; Thermal degradation; Thermal resistance; Thermal stresses; Uniaxial strain
• DOI: 10.1109/VTSA.2008.4530825
• ISBN: 9781424416141; 1424416140
• ISSN: 1524-766X

In this paper, we have systematically investigated the impact of the thermal-induced stress relaxation on biaxially strained silicon-on-insulator (SSOI) CMOS. We found that STI anneal would degrade nMOS drive current by 12% but improve pMOS by 17% in long channel SSOI devices. However, skipping LDD anneal would increase extension resistance and cause performance degradation. In addition, it is found that narrow-width devices suffer more serious thermal strain relaxation. After optimizing the thermal process, we successfully demonstrate enhanced sSOI nMOS with 65% transconductance gain at L = 1 um and 15% drive current improvement at L = 40 nm over SOI nMOS.