Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis

• Published in: 2018 28th International Conference on Field Programmable Logic and Applications (FPL) pp. 280 - 2806
• Main Authors: Oppermann, Julian, Reuter-Oppermann, Melanie, Sommer, Lukas, Sinnen, Oliver, Koch, Andreas
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2018
• Subjects: complexity reduction; Delays; high level synthesis; modulo scheduling; Optimal scheduling; Processor scheduling; Runtime; Schedules; Throughput; VLIW
• ISSN: 1946-1488
• DOI: 10.1109/FPL.2018.00055

Modulo scheduling is a key throughput optimisation when compiling for VLIW architectures, which has been applied successfully to high-level synthesis (HLS) of hardware accelerators in the past. However, problem instances in the HLS context usually have larger and denser dependence graphs and may contain many simple operations that are not subject to resource constraints, causing long runtimes with VLIW-centric modulo schedulers. We propose a complexity-reduction approach for existing exact modulo schedulers that retains their ability to compute provably optimal schedules, but shortens their runtime on typical HLS instances. The basic idea is to simplify a problem instance's dependence graph by abstracting entire subgraphs of non-critical operations with a single edge, then schedule this reduced problem comprising only the critical operations. A solution obtained for the reduced problem can be easily completed to a solution for the original problem. Applied to the well-known, originally VLIW-centric, and exact ILP formulation by Eichenberger and Davidson, we show a mean speedup of 4.37x for 21 large instances, which makes it competitive again with the recently proposed, HLS-tailored Moovac formulation. As both formulations show different problem-dependent strengths and weaknesses, these insights are a first step towards an oracle that selects the most promising scheduler for a given problem instance.