Thermal analysis of 3D packaging with a simplified thermal resistance network model and finite element simulation

• Published in: 2010 11th International Conference on Electronic Packaging Technology and High Density Packaging pp. 737 - 741
• Main Authors: Zhaohui Chen, Xiaobing Luo, Sheng Liu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2010
• Subjects: Conductivity; Copper; Electronic packaging thermal management; Thermal conductivity; Thermal resistance; Through-silicon vias
• ISBN: 9781424481408; 1424481406
• DOI: 10.1109/ICEPT.2010.5582840

Analytical solution is established to calculate equivalent thermal resistances of the through silicon via (TSV) structure in both z direction and x y directions and is verified by the finite element simulation. The effects of the structural parameters such as the thickness of die, the diameter of copper via and the pitch of the copper via on the equivalent thermal conductivity of composite TSV structure have been investigated. It is found that the thermal conductivity in z direction increases with the diameter of copper via and decrease with pitch of TSV and keep constant with the thickness. While the thermal conductivity of in x y directions increases with the pitch of TSV and decreases with the thickness of the TSV and copper diameter. The SiO 2 layer with thermal conductivity of only about 1.57 W/mK plays an important role in determining the equivalent thermal conductivity of TSV composite structure. A thermal resistance network model for the stacked-die package is built up to estimate the junction temperature. FEM simulation is conducted to investigate the thermal performance of the stacked-die package simplified with equivalent thermal conductivity. With equivalent thermal properties and thermal resistance network model the thermal performance of the stacked-die package can be estimated quickly and to obtain the optimization package structure of the high thermal dissipation.