Maximizing MLC NAND lifetime and reliability in the presence of write noise

• Published in: 2012 IEEE International Conference on Communications (ICC) pp. 3752 - 3756
• Main Authors: Peleato, B., Agarwal, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2012
• Subjects: Approximation methods; Ash; Bit error rate; Noise; Programming; Reliability

The aggressive scaling of the NAND flash technology has led to write noise becoming the dominant source of disturbance in the currently shipping sub-30 nm MLC NAND memories. Write noise can be mitigated by reducing the magnitude of the voltage levels programmed into the cells, which additionally tra...