Advances in DSP design tool flows for FPGAs

• Published in: 2010 - MILCOM 2010 MILITARY COMMUNICATIONS CONFERENCE pp. 2041 - 2046
• Main Author: Jervis, M
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2010
• Subjects: Algorithm design and analysis; Clocks; Digital signal processing; Field programmable gate arrays; Hardware design languages; Pipeline processing; Radio frequency
• DOI: 10.1109/MILCOM.2010.5680454
• ISBN: 9781424481781; 1424481783
• ISSN: 2155-7578

This paper highlights recent advances in digital signal processing (DSP) design tools for Field-Programmable Gate Arrays (FPGAs), concentrating on model-based design high-level synthesis. Next generation FPGA model-based design tools provide a mechanism for abstracted design definition at the algorithmic rather than implementation level. The tools make use of FPGA structural and timing knowledge, and of mathematical and graph theory techniques to optimize and technology map the algorithm to a pipelined FPGA implementation, controlled by high level parameters and threshold settings. Such tools allow simple design space exploration and retargeting of algorithms to different device families. This design-once and retarget as required method improves productivity over manual hardware description language (HDL) coding, especially for projects which are subject to change. The simple design style, optimized generated hardware and productivity in design change and implementation exploration are highlighted with two examples; a direct radio-frequency (RF) radar design and a simple 8 by 8 beamforming design.