Evaluation of compensation techniques for CMOS operational amplifier design

This paper presents and compares two CMOS (complementary metal oxide semiconductor) operational amplifier (op-amp) designs. Each op-amp is based on a two-stage rail-to-rail output where the first stage is a differential input with folded cascode and the second stage forms a class-AB amplifier. Each...

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Bibliographic Details
Published in2018 International Conference on IC Design & Technology (ICICDT) pp. 5 - 8
Main Authors Zaidi, Muhaned, Grout, Ian, A'ain, Abu Khari
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Capacitance
Capacitors
Circuit stability
CMOS amplifier
Frequency response
Gain
indirect Miller
Miller compensation
negative Miller
Power supplies
Rail-to-rail output
Transistors
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Summary:This paper presents and compares two CMOS (complementary metal oxide semiconductor) operational amplifier (op-amp) designs. Each op-amp is based on a two-stage rail-to-rail output where the first stage is a differential input with folded cascode and the second stage forms a class-AB amplifier. Each opamp design incorporates different compensation techniques. The first op-amp uses negative Miller compensation around the first stage and conventional Miller compensation is used around the second stage. The second op-amp also utilizes negative Miller around the first stage, but with indirect Miller between the output node of the second stage and cascode node of the first stage. The purpose of this work was to evaluate the DC gain, unity gain frequency (UGF) and phase margin (PM) achieved using the different compensation techniques in simulation and test results from physical prototype devices using a 0.35 μm CMOS technology when operating on a single rail +2.5V and +1.8 V power supply.
DOI:10.1109/ICICDT.2018.8399722