45 nm-CMOS Temperature Sensor Using 2-Stage Vernier Technique

This paper presents the architecture of temperature sensor which consists of an improved pulse generator and a high resolution time-to-digital converter (TDC) based on 2-stage Vernier delay line. The improved pulse generator generates a pulse width proportional to the temperature by using temperatur...

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Bibliographic Details
Published in2018 4th International Conference on Green Technology and Sustainable Development (GTSD) pp. 693 - 695
Main Author Vo, Minh-Huan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2018
Subjects
Delay lines
Delays
high resolution
Inverters
Logic gates
Pulse generation
Temperature dependence
temperature sensor
Temperature sensors
Time-to-digital converter
Vernier delay line
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Summary:This paper presents the architecture of temperature sensor which consists of an improved pulse generator and a high resolution time-to-digital converter (TDC) based on 2-stage Vernier delay line. The improved pulse generator generates a pulse width proportional to the temperature by using temperature dependent delay line and temperature insensitive delay line. The pulse width is converted to a corresponding digital code by time to- digital (TDC) converter. Simulation results using an analog design environment Cadence tool indicate that the method can be employed to calibrate high-resolution TDCs with high accuracy. The time-to-digital converter circuit is designed in 45nm CMOS technology and achieves resolution less than 5ps.
DOI:10.1109/GTSD.2018.8595605