Reconfigurable Threshold Logic Gates using memristive devices

We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-...

Full description

Saved in:
Bibliographic Details
Published in2012 IEEE Subthreshold Microelectronics Conference pp. 1 - 3
Main Authors Thanh Tran, Rothenbuhler, A., Smith, E. H. B., Saxena, V., Campbell, K. A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2012
Subjects
CMOS integrated circuits
Integrated circuit modeling
Logic gates
Memristors
Programming
Resistance
threshold logic circuits
Threshold voltage
Online AccessGet full text
ISBN1467315869
9781467315869
DOI10.1109/SubVT.2012.6404301

Cover

Abstract We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.
AbstractList We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.
Author Saxena, V.
Rothenbuhler, A.
Thanh Tran
Smith, E. H. B.
Campbell, K. A.
Author_xml – sequence: 1
  surname: Thanh Tran
  fullname: Thanh Tran
  organization: Electr. & Comput. Eng. Dept., Boise State Univ., Boise, ID, USA
– sequence: 2
  givenname: A.
  surname: Rothenbuhler
  fullname: Rothenbuhler, A.
  organization: Electr. & Comput. Eng. Dept., Boise State Univ., Boise, ID, USA
– sequence: 3
  givenname: E. H. B.
  surname: Smith
  fullname: Smith, E. H. B.
  email: EBarneySmith@boisestate.edu
  organization: Electr. & Comput. Eng. Dept., Boise State Univ., Boise, ID, USA
– sequence: 4
  givenname: V.
  surname: Saxena
  fullname: Saxena, V.
  email: VishalSaxena@BoiseState.edu
  organization: Electr. & Comput. Eng. Dept., Boise State Univ., Boise, ID, USA
– sequence: 5
  givenname: K. A.
  surname: Campbell
  fullname: Campbell, K. A.
  organization: Electr. & Comput. Eng. Dept., Boise State Univ., Boise, ID, USA
BookMark eNo1j89KxDAYxCMq6K59Ab3kBVq_NEmTHDzI4q5CQdDqdUmbr91I_0jTLvj2FlxPw2-GGZgVueiHHgm5ZZAwBub-fS4_iyQFliaZAMGBnZHIKM1EpjiTWqbnZPUPmbkiUQhfALCUFfDsmjy8YTX0tW_m0ZYt0uIwYjgMraP50PiK7uyEgc7B9w3tsBt9mPwRqcOjrzDckMvatgGjk67Jx_ap2DzH-evuZfOYx54pOcVO1ZUyQpalK6W2SnOpuUi1VopllSkd12AkLj6IzFbG1WDUEhsLBhfka3L3t-sRcf89-s6OP_vTY_4LU69LVw
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/SubVT.2012.6404301
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781467315852
1467315877
9781467315876
1467315850
EndPage 3
ExternalDocumentID 6404301
Genre orig-research
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
AAWTH
ADFMO
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
IEGSK
IERZE
OCL
RIE
RIL
ID FETCH-LOGICAL-i175t-d7fc7945bbdb58a78358342887716c9bd38095e783046ac9df0972889a09ec9d3
IEDL.DBID RIE
ISBN 1467315869
9781467315869
IngestDate Wed Aug 27 03:00:07 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i175t-d7fc7945bbdb58a78358342887716c9bd38095e783046ac9df0972889a09ec9d3
PageCount 3
ParticipantIDs ieee_primary_6404301
PublicationCentury 2000
PublicationDate 2012-Oct.
PublicationDateYYYYMMDD 2012-10-01
PublicationDate_xml – month: 10
  year: 2012
  text: 2012-Oct.
PublicationDecade 2010
PublicationTitle 2012 IEEE Subthreshold Microelectronics Conference
PublicationTitleAbbrev SubVT
PublicationYear 2012
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0001107036
Score 1.5610063
Snippet We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms CMOS integrated circuits
Integrated circuit modeling
Logic gates
Memristors
Programming
Resistance
threshold logic circuits
Threshold voltage
Title Reconfigurable Threshold Logic Gates using memristive devices
URI https://ieeexplore.ieee.org/document/6404301
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV09T8MwELVKJyZALeJbHhhJWjtOYg9MiKpCKmJoUbcqti9VhZqiNunAr8fnNK1ADCxR7CHyR-zzO793R8g9Oux5P4ZApMI9gGeBEloGEY8lFwBJrlDgPHpNhhPxMo2nLfKw18IAgCefQYiv_i7frkyFrrJegqFgUKx15IBbrdU6-FMY_ryJ124lacRimagmpFNTbkQzfdVzy_J9jMwuHu6--iO9ircugxMyatpVk0o-wqrUofn6FbLxvw0_Jd2Djo--7S3UGWlB0SGPiDiLfDGv1iibomM3mxu8hKKYd9lQ9KdtKPLh53QJS78JbIFa8HtKl0wGz-OnYbBLohAs3MmgDGyaG7fmYq2tjmWGjh4ZOcwhU4eUjNI2ku6UBa7eIeXMKJtjQB8pVdZX4IrROWkXqwIuCNVWSK4BGEtzoUWWWZYzI7gBxY1h-SXpYNdnn3WcjNmu11d_V1-TYxz-mhh3Q9rluoJbZ-BLfedn9htALqFC
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV09T8MwELWqMsAEqEV844GRpI3jJPbAhKgKtBVDirpVsX2pKtQUtQkDvx5f0rQCMbBEsYfI1sU-3_O9d4TcImDPugE4POL2ASxxJFfC8VkgGAcIU4kE5-Eo7I_58ySYNMjdlgsDAGXyGbj4Wt7lm6UuECrrhCgFg2StPev3uazYWjtExcPfNyzZW2Hke4EIZS3qVLdr2kxXduzCfIsxt4u5m-_-KLBS-pfeIRnWI6vSSt7dIleu_vol2vjfoR-R9o7JR1-3PuqYNCBrkXuMObN0PitWSJyisbXnGq-hKFZe1hQRtTXFjPgZXcCi3AY-gRood5U2Gfce44e-symj4Mzt2SB3TJRqu-oCpYwKRIJQj_Bt1CEiGytpqYwv7DkLbL-NlRMtTYqSPkLIpCvBNv0T0syWGZwSqgwXTAF4XpRyxZPEeKmnOdMgmdZeekZaOPXpR6WUMd3M-vzv7huy34-Hg-ngafRyQQ7QFFWa3CVp5qsCrqy7z9V1aeVv7Z6kkg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2012+IEEE+Subthreshold+Microelectronics+Conference&rft.atitle=Reconfigurable+Threshold+Logic+Gates+using+memristive+devices&rft.au=Thanh+Tran&rft.au=Rothenbuhler%2C+A.&rft.au=Smith%2C+E.+H.+B.&rft.au=Saxena%2C+V.&rft.date=2012-10-01&rft.pub=IEEE&rft.isbn=9781467315869&rft.spage=1&rft.epage=3&rft_id=info:doi/10.1109%2FSubVT.2012.6404301&rft.externalDocID=6404301
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781467315869/lc.gif&client=summon&freeimage=true
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781467315869/mc.gif&client=summon&freeimage=true
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781467315869/sc.gif&client=summon&freeimage=true