SET Emulation Under a Quantized Delay Model

• Published in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) pp. 68 - 78
• Main Authors: Valderas, M.G., Cardenal, R.F., Celia Lopez Ongil, Garcia, M.P., Entrena, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2007
• Subjects: Circuit faults; Circuit simulation; Clocks; Delay effects; Emulation; Field programmable gate arrays; Flip-flops; Logic; Performance analysis; Voltage
• DOI: 10.1109/DFT.2007.49
• ISBN: 9780769528854; 0769528856
• ISSN: 1550-5774

Single event transient (SET) fault analysis is usually performed trough digital simulation at the gate level. However, this method cannot be used for large fault injection campaigns, since gate level simulation is quite slow. In this paper, we propose an approach to build an FPGA based SET emulator, which implements a quantized delay model of the circuit under evaluation. Experimental results demonstrate that the quantized delay model produces accurate results and can be easily captured in a FPGA. The proposed approach can be automated to increase SET fault analysis performance by three orders of magnitude with respect to simulation.