Modelling of threshold voltage shift in pulsed NBT stressed P-channel power VDMOSFETs

• Published in: 2017 IEEE 30th International Conference on Microelectronics (MIEL) pp. 147 - 151
• Main Authors: Dankovic, D., Manic, I., Stojadinovic, N., Prijic, Z., Djoric-Veljkovic, S., Davidovic, V., Prijic, A., Paskaleva, A., Spassov, D., Golubovic, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2017
• Subjects: Degradation; Integrated circuit modeling; Negative bias temperature instability; Resistors; Stress; Thermal variables control; Threshold voltage
• DOI: 10.1109/MIEL.2017.8190089
• ISBN: 153862561X; 9781538625613

Negative bias temperature instabilities in commercial IRF9520 p-channel power VDMOSFETs under both static and pulsed bias stress conditions were studied. The pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, as a consequence of partial recovery during the low level of pulsed gate voltage. Furthermore, it was shown that the quantitative differences between static and pulsed NBT stress depend on both stress duty cycle and frequency, and the differences become more significant as the duty cycle decreases and frequency increases. These results indicated that more emphasis needs to be placed on pulsed negative bias temperature stressing. Modelling of threshold voltage shifts induced by pulsed negative bias temperature stress has been done on the bases of experimental results, and equivalent electrical circuit has been proposed.