Fault tree analysis using stochastic logic: A reliable and high speed computing

• Published in: 2011 Proceedings - Annual Reliability and Maintainability Symposium pp. 1 - 6
• Main Authors: Aliee, H, Zarandi, H R
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2011
• Subjects: fault tree; Fault trees; Logic gates; Mathematical model; Monte Carlo methods; Monte Carlo Simulation; Reliability; stochastic logic; Stochastic processes; Tunneling magnetoresistance
• ISBN: 9781424488575; 1424488575
• ISSN: 0149-144X
• DOI: 10.1109/RAMS.2011.5754466

Fault tree analysis is a widespread-use approach for analyzing reliability and safety in critical systems. In this paper, a new approach is introduced to analyze fault trees based on stochastic logic. Applying stochastic logic makes it possible to present floating point numbers as bit streams, in which the quantity of `1' bits is proportional to the evaluated number. In addition, using stochastic logic-based circuits to analyze fault-trees makes the circuits reliable against possible fau lts in the computation circuitry. Moreover, stochastic logic-based fault-tree analysis is fast, since both static and dynamic fau lt tree gates can be easily mapped to their equivalents in stochastic logic, and then be implemented on hardware. The method is based on Monte Carlo algorithm, in which, the failure rates of basic components of a given system are computed at different time slots. At the next step, the whole system's failure rate could be calculated using the stochastic circuitry implemented on hardware. Repeating the experiments for several time slots, results in the reliability-time plot of the system. The experimental results show that this technique is fast and reliable, with negligible calculation error.