A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application - Lue, Hang-Ting; Chen, Weichen; Chang, Hung-Sheng; Wang, Keh-Chung; Lu, Chih-Yuan (2018 IEEE Symposium on VLSI Technology, 2018)
An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.