Stochastic TDC architecture with self-calibration - Ito, S; Nishimura, S; Kobayashi, H; Uemori, S; Tan, Y; Takai, N; Yamaguchi, T J; Niitsu, K (APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010)
This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4) Self-testing for reliability requirements. These features can be implemented with an advanced fine CMOS process using digital design methodology. The circuit structure and operation are described, and MATLAB simulation results are presented.