Novel wafer dicing and chip thinning technologies realizing high chip strength

• Published in: 56th Electronic Components and Technology Conference 2006 p. 5 pp.
• Main Authors: Takyu, S., Kurosawa, T., Shimizu, N., Harada, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Blades; Packaging machines; Semiconductor device manufacture; Semiconductor device measurement; Semiconductor device packaging; Semiconductor devices; Stacking; Surface cracks; Testing; Transportation
• ISBN: 1424401526; 9781424401529
• ISSN: 0569-5503
• DOI: 10.1109/ECTC.2006.1645874

As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thickness of 50 to 200 mum, such damage has to be avoided. In this study, the relationship between chip residue damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1312 MPa are described