Digital background calibration technique for pipeline ADCs with multi-bit stages

This paper presents a technique for background calibration of pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations of the LMS algorithm have been studied, concluding that the traditional SS-LMS (sign-sign LMS) algorithm has inherent convergence problems in hi...

Full description

Saved in:
Bibliographic Details
Published in16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings pp. 317 - 322
Main Authors Gines, A.J., Peralias, E.J., Rueda, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Online AccessGet full text

Cover

Loading…
Abstract This paper presents a technique for background calibration of pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations of the LMS algorithm have been studied, concluding that the traditional SS-LMS (sign-sign LMS) algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering an SD-LMS (sign-data LMS) implementation.
AbstractList This paper presents a technique for background calibration of pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations of the LMS algorithm have been studied, concluding that the traditional SS-LMS (sign-sign LMS) algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering an SD-LMS (sign-data LMS) implementation.
Author Peralias, E.J.
Gines, A.J.
Rueda, A.
Author_xml – sequence: 1
  givenname: A.J.
  surname: Gines
  fullname: Gines, A.J.
  organization: Instituto de Microelectonica de Sevilla, Centro Nacional de Microelectron., Sevilla, Spain
– sequence: 2
  givenname: E.J.
  surname: Peralias
  fullname: Peralias, E.J.
  organization: Instituto de Microelectonica de Sevilla, Centro Nacional de Microelectron., Sevilla, Spain
– sequence: 3
  givenname: A.
  surname: Rueda
  fullname: Rueda, A.
  organization: Instituto de Microelectonica de Sevilla, Centro Nacional de Microelectron., Sevilla, Spain
BookMark eNotj8tKAzEYRgMqaGtfQDd5gam5TSZZ1qnVQkFBBXcll7_TX6czdZIivr0F-20OnMWBb0TOu74DQm44m3LO7N3rfV0vp4IxOeVCCqOqMzJilbbl0dmPSzJJ6ZMdp0plNL8iL3NsMLuWehe-mqE_dJEG16IfXMa-oxnCtsPvA9BNP9A97qHFDuhsXif6g3lLd4c2Y-Ex05RdA-maXGxcm2By4pi8Lx7e6qdi9fy4rGerAnlV5sKIYIXVPFpfMitlDNqoELhWzHvPlQjAZDBWRxY992AUGKFj3HhwWqoox-T2v4sAsN4PuHPD7_p0Wv4Btg5QDQ
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/SBCCI.2003.1232847
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library Online
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EndPage 322
ExternalDocumentID 1232847
GroupedDBID 6IE
6IK
6IL
AAJGR
AAVQY
ACM
ADPZR
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
GUFHI
IERZE
LHSKQ
OCL
RIB
RIC
RIE
RIL
ID FETCH-LOGICAL-i175t-82c92961d9b50933dc684cc1640bbb142ce03c896d0db1be84e826ddfbea634d3
IEDL.DBID RIE
ISBN 076952009X
9780769520094
IngestDate Wed Jun 26 19:20:35 EDT 2024
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i175t-82c92961d9b50933dc684cc1640bbb142ce03c896d0db1be84e826ddfbea634d3
PageCount 6
ParticipantIDs ieee_primary_1232847
PublicationCentury 2000
PublicationDate 20030000
PublicationDateYYYYMMDD 2003-01-01
PublicationDate_xml – year: 2003
  text: 20030000
PublicationDecade 2000
PublicationTitle 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings
PublicationTitleAbbrev SBCCI
PublicationYear 2003
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0000454861
Score 1.3535492
Snippet This paper presents a technique for background calibration of pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations of...
SourceID ieee
SourceType Publisher
StartPage 317
SubjectTerms Adaptive arrays
Analog-digital conversion
Calibration
Convergence
Energy consumption
Hardware
Least squares approximation
Pipelines
Radar antennas
Signal processing algorithms
Title Digital background calibration technique for pipeline ADCs with multi-bit stages
URI https://ieeexplore.ieee.org/document/1232847
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV09T8MwELXaTkyAWsS3PDCSNKGOa4-QggpSUSWo1K3K2deqqpRWNF349ZydJgjEwJZksKyz5Lv3cu8dYzfSxhkKCwEokQQCTRKAiEQw1xYIjM1BGwcUR69yOBEv02TaYLe1FgYRffMZhu7R_8u3a7NzVFnXpX-6TZus2de61GrVfIqzklMyLpG59mZClcFO9S4q0Uyku28Pafrs7UDD_ao_xqv47PJ0yEbVvsqmklW4KyA0n78sG_-78SPW-dbx8XGdoY5ZA_M2Gw-WCzcphENmVk7UkVtOB-VgszskXru6cqpn-Wa5cYp15PeDdMsda8t9DyIh6oJTZbnAbYdNnh7f02Gwn6sQLKlYKAJ1Z6gokrHVkDhCwxqphDEEnCIARwq5GWJGaWkjCzGgEkggxNo5YCZ7wvZOWCtf53jKOBU0NtE9Q7BD0pWbgZWKoi0h6WM_AXPG2i4as01pnTHbB-L8788X7MD3ynmG45K1io8dXlHOL-DaH_YXFfKolQ
link.rule.ids 310,311,783,787,792,793,799,4057,4058,27937,55086
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3PT8IwFG4QD3pSA8bf9uDRjU260h51aECBkAgJN7LXFkJIBpFx8a_3tWMzGg_eth2a5jXp-763932PkDuuw8QwDR4IFnnMqMgDFjBvJjUgGZuBVJYo9ge8M2avk2hSIfelFsYY45rPjG8f3b98vVJbWypr2PSPt-ke2UdcLXiu1iorKtZMTvAw5-bS2QkVFjvFOytkM4FsvD_FcdcZgvq7dX8MWHH55eWI9Iud5W0lS3-bga8-f5k2_nfrx6T-reSjwzJHnZCKSWtk2F7M7awQColaWllHqikelSXO9pho6etKEdHS9WJtNeuGPrbjDbV1W-q6EJFTZxSx5dxs6mT88jyKO95usoK3QLiQeeJBISzioZYQ2ZKGVlwwpZA6BQC2LGSniCkhuQ40hGAEM0hDtJ6BSXiT6eYpqaar1JwRipBGR7KpkHhwvHQT0FxgtDlELdOKQJ2Tmo3GdJ2bZ0x3gbj4-_MtOeiM-r1przt4uySHrnPO1TuuSDX72JprRAAZ3LiD_wIbKavg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=16th+Symposium+on+Integrated+Circuits+and+Systems+Design%2C+2003.+SBCCI+2003.+Proceedings&rft.atitle=Digital+background+calibration+technique+for+pipeline+ADCs+with+multi-bit+stages&rft.au=Gines%2C+A.J.&rft.au=Peralias%2C+E.J.&rft.au=Rueda%2C+A.&rft.date=2003-01-01&rft.pub=IEEE&rft.isbn=9780769520094&rft.spage=317&rft.epage=322&rft_id=info:doi/10.1109%2FSBCCI.2003.1232847&rft.externalDocID=1232847
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9780769520094/lc.gif&client=summon&freeimage=true
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9780769520094/mc.gif&client=summon&freeimage=true
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9780769520094/sc.gif&client=summon&freeimage=true