A power-efficient asynchronous circuit style with selective input-channel restoring

A new power efficient asynchronous circuit design is presented in this paper. By using new input channel restoring circuits and function block partitioning technique to restore only asserted input channels, the transistor area used in each asynchronous logic function unit and thus the load capacitan...

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Bibliographic Details
Published in2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 25 - 28
Main Authors Chin-Khai Tang, Yi-Chang Lu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2013
Subjects
Asynchronous circuits
Capacitance
Delays
Inverters
Logic gates
Power demand
Transistors
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Summary:A new power efficient asynchronous circuit design is presented in this paper. By using new input channel restoring circuits and function block partitioning technique to restore only asserted input channels, the transistor area used in each asynchronous logic function unit and thus the load capacitance can be effectively minimized. As a result, the circuit power consumption can be reduced. Our simulation results show that, when compared to STFB circuits, the new asynchronous circuit consumes at least 26% less power. Thus, by applying the new asynchronous circuit design technique, low power consumption and area usage can be achieved.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2013.6674576