Key enabling processes for more-than-moore technologies - Lindner, P.; Glinsner, T.; Uhrmann, T.; Dragoi, V.; Plach, T.; Matthias, T.; Pabo, E.; Wimplinger, M. (2012 IEEE International SOI Conference (SOI), 2012)
The continuation of Moore's law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards "More Than Moore" with relatively smaller capital investment. Recent announcements from leading image sensor and memory manufacturers show that 3D-ICs are finally moving into high-volume manufacturing (HVM) putting "More Than Moore" in reality. Wafer bonding is the enabling process technology to make this happen. Two of the key wafer bonding techniques - low temperature fusion bonding as well as temporary bonding and de-bonding are the major subject of this contribution, introducing basic process flows and working principles for their CMOS integration.