A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding

This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of- the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid th...

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Bibliographic Details
Published in2011 18th IEEE International Conference on Image Processing pp. 393 - 396
Main Authors Shafique, Muhammad, Tufek, Adnan Orcun, Henkel, Jorg
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2011
Subjects
Computer architecture
Context
Encoding
Entropy Coding
H.264/AVC
Hardware
Hardware Architecture
Image coding
Indexes
Throughput
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Summary:This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of- the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid the extra looping logic in CAVLC. This provides significant performance improvement compared to state-of-the-art (saving of 16 cycles per 4×4 sub-block compared to [2]). Furthermore, our hardware architecture employs parallel processing of Trailing Ones (which is one of the inherently sequential steps in CAVLC) and encodes levels and runs in parallel in the same pipeline stage. An intelligent bitstream writing logic generates the compliant bitstream. Compared to state-of-the-art, our proposed hardware architecture requires 72% reduced area and achieves 2× higher throughput, while processing HD1080p@30fps.
ISBN:1457713047
9781457713040
ISSN:1522-4880
2381-8549
DOI:10.1109/ICIP.2011.6116532