Copper die bumps (first level interconnect) and low-K dielectrics in 65nm high volume manufacturing

The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have made integrating copper bumps challenging, i.e...

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Bibliographic Details
Published in56th Electronic Components and Technology Conference 2006 p. 5 pp.
Main Authors Yeoh, A., Chang, M., Pelto, C., Tzuen-Luh Huang, Balakrishnan, S., Leatherman, G., Agraharam, S., Guotao Wang, Zhiyong Wang, Chiang, D., Stover, P., Brandenburger, P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Assembly
Conductivity
Copper
Dielectrics
Electronics packaging
Flip chip
Lead
Manufacturing
Mechanical factors
Passivation
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ISBN1424401526
9781424401529
ISSN0569-5503
DOI10.1109/ECTC.2006.1645872

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Summary:The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump critical dimension (CD) floor, continued downward scaling of passivation opening size, a drastically simplified underbump metallization (UBM) scheme that projects to improved electromigration resistance, and extensions to higher 10 densities. This paper will discuss some of these gains
ISBN:1424401526
9781424401529
ISSN:0569-5503
DOI:10.1109/ECTC.2006.1645872