A Multi-Mode Visual Recognition Hardware Accelerator for AR/MR Glasses

A multi-mode visual recognition hardware accelerator for AR/MR glasses is designed in this paper. The accelerator supports state-of-the-art deep neural networks, including DNN, CNN, RNN and LSTM. To achieve higher utilization rate of computational components, the accelerator supports two mapping mod...

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Published inIEEE International Conference on Circuits and Systems (Online) pp. 1 - 5
Main Authors Yunhui Zhu, Yaohua Zuo, Tong Zhou, Guoping Fan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2018
Subjects
Online AccessGet full text
ISSN2379-447X
DOI10.1109/ISCAS.2018.8350918

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Abstract A multi-mode visual recognition hardware accelerator for AR/MR glasses is designed in this paper. The accelerator supports state-of-the-art deep neural networks, including DNN, CNN, RNN and LSTM. To achieve higher utilization rate of computational components, the accelerator supports two mapping modes of neural networks to physical computational structures in a single PE (Processing Engine) array: a) 2D systolic flow of both filter and image data, b) each neural network output maps to a PE. The accelerator adaptively chooses the more efficient mapping mode layer by layer, achieving a higher PE utilization rate than single mapping mode accelerators. When benchmarking with Inception-v4 network, the accelerator's PE utilization rate is 79.5%, which is 20 points higher than state-of-the-art embedded accelerators. Higher PE utilization rate contributes to lower latency, higher throughput, less power consumption and smaller chip area. When benchmarking with AlexNet, the accelerator processes 108 images per second, which fully meets the real-time requirement for AR/MR applications.
AbstractList A multi-mode visual recognition hardware accelerator for AR/MR glasses is designed in this paper. The accelerator supports state-of-the-art deep neural networks, including DNN, CNN, RNN and LSTM. To achieve higher utilization rate of computational components, the accelerator supports two mapping modes of neural networks to physical computational structures in a single PE (Processing Engine) array: a) 2D systolic flow of both filter and image data, b) each neural network output maps to a PE. The accelerator adaptively chooses the more efficient mapping mode layer by layer, achieving a higher PE utilization rate than single mapping mode accelerators. When benchmarking with Inception-v4 network, the accelerator's PE utilization rate is 79.5%, which is 20 points higher than state-of-the-art embedded accelerators. Higher PE utilization rate contributes to lower latency, higher throughput, less power consumption and smaller chip area. When benchmarking with AlexNet, the accelerator processes 108 images per second, which fully meets the real-time requirement for AR/MR applications.
Author Guoping Fan
Tong Zhou
Yunhui Zhu
Yaohua Zuo
Author_xml – sequence: 1
  surname: Yunhui Zhu
  fullname: Yunhui Zhu
  email: yunhui.zhu@samsung.com
  organization: Samsung R&D Inst. China-Beijing, Beijing, China
– sequence: 2
  surname: Yaohua Zuo
  fullname: Yaohua Zuo
  email: yaohua.zuo@samsung.com
  organization: Samsung R&D Inst. China-Beijing, Beijing, China
– sequence: 3
  surname: Tong Zhou
  fullname: Tong Zhou
  email: t1102.zhou@samsung.com
  organization: Samsung R&D Inst. China-Beijing, Beijing, China
– sequence: 4
  surname: Guoping Fan
  fullname: Guoping Fan
  email: gp.fan@samsung.com
  organization: Samsung R&D Inst. China-Beijing, Beijing, China
BookMark eNotj81KAzEURqMo2Na-gG7yAtPmTpKbzHIo9gc6CK2KuxIzNxIZZ2QyRfr2Fuzi48BZHPjG7KbtWmLsAcQMQBTzzX5R7me5ADuzUosC7BUbg5YWlbWgrtkol6bIlDLvd2ya0pcQQoIxGtWILUteHZshZlVXE3-L6egaviPffbZxiF3L166vf11PvPSeGurd0PU8nFfu5tWOrxqXEqV7dhtck2h64YS9Lp9eFuts-7zaLMptFsHoIUOLBpVzWGvMDQQsPpwMKlgTApLVEsDLIgdVe-lqBMydl8p4a5A0nuWEPf53IxEdfvr47frT4XJb_gFjzExu
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/ISCAS.2018.8350918
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 1538648814
9781538648810
EISSN 2379-447X
EndPage 5
ExternalDocumentID 8350918
Genre orig-research
GroupedDBID 6IE
6IF
6IH
6IK
6IL
6IN
AAJGR
ABLEC
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
IPLJI
OCL
RIE
RIL
RIO
ID FETCH-LOGICAL-i175t-686764aa6d56271f69ba3f4f87ff6e85311c39214dc3ad6162ac347c876e56dc3
IEDL.DBID RIE
IngestDate Wed Aug 27 08:32:58 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i175t-686764aa6d56271f69ba3f4f87ff6e85311c39214dc3ad6162ac347c876e56dc3
PageCount 5
ParticipantIDs ieee_primary_8350918
PublicationCentury 2000
PublicationDate 2018-May
PublicationDateYYYYMMDD 2018-05-01
PublicationDate_xml – month: 05
  year: 2018
  text: 2018-May
PublicationDecade 2010
PublicationTitle IEEE International Conference on Circuits and Systems (Online)
PublicationTitleAbbrev ISCAS
PublicationYear 2018
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0003177564
Score 2.0264494
Snippet A multi-mode visual recognition hardware accelerator for AR/MR glasses is designed in this paper. The accelerator supports state-of-the-art deep neural...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms AR/MR glasses
Arrays
Bandwidth
Clocks
Engines
Hardware
hardware accelerator
multi-mode
Neural networks
PE utilization rate
visual recognition
Visualization
Title A Multi-Mode Visual Recognition Hardware Accelerator for AR/MR Glasses
URI https://ieeexplore.ieee.org/document/8350918
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1Na8JAEB3UU3vph5Z-s4cem2jMZpIcg9TagqVoLd5ks5mAtMSiCYX--s4maj_oobewEBJ2NnmPmfdmAK5CqRKUhBZjnbaY__Mn5WFsucTgE5L20rJd0_ABBxN5P_WmNbjeemGIqBSfkW0uy1p-stCFSZW1mS0wvAV1qPMxq7xa23wK46Dvodz4Yjph-27ci8ZGvBXY6xt_TFApAaS_B8PNoyvdyItd5LGtP351Zfzvu-1D68uqJx63IHQANcoOYfdbl8Em9CNR2mwtM_dMPM9XhXoVo41waJEJU71_V0sSkdaMQmXhXTCZFdGoPRyJW0OwadWCSf_mqTew1uMTrDlzgtzCAH2USmHCHMd3Ugxj5aYyDfw0RWKYdhzN7MiRiXY5YA52lXalr_n_SB7y4hE0skVGxyAcL5WOyT_5MUoOX9jxVOAnAVEYh12FJ9A0OzJ7qzpkzNabcfr38hnsmKhUssFzaOTLgi4Y2vP4sozpJ9MsoZg
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LS8NAEB5qPagXH634dg8eTdo0m01yDMXaalukD-mtbDYTKEoqbYLgr3c2aesDD96WhSVhh-T7mPm-GYAbn8tIcBQGYZ0yiP_TJ-WI0LCRwMdH5cR5u6ZeX7TH_GHiTEpwu_HCIGIuPkNTL_NafjRXmU6V1YgtELx5W7BNuM-dwq21yagQErqO4GtnTN2vdYbNYKjlW565OvpjhkoOIa196K0fXihHXswsDU318asv43_f7gCqX2Y99rSBoUMoYXIEe9_6DFagFbDcaGvoyWfsebbM5CsbrKVD84Tp-v27XCALlCIcykvvjOgsCwa13oDda4qNyyqMW3ejZttYDVAwZsQKUkN4whVcShERy3GtWPihtGMee24cCySgtixF_MjikbIpZJZoSGVzV9EfEh1Bm8dQTuYJngCznJhbOgPlhoJTAP26Iz038hD90G9IcQoVfSPTt6JHxnR1GWd_b1_DTnvU6067nf7jOezqCBUiwgsop4sMLwno0_Aqj-8nfGqk5Q
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=IEEE+International+Conference+on+Circuits+and+Systems+%28Online%29&rft.atitle=A+Multi-Mode+Visual+Recognition+Hardware+Accelerator+for+AR%2FMR+Glasses&rft.au=Yunhui+Zhu&rft.au=Yaohua+Zuo&rft.au=Tong+Zhou&rft.au=Guoping+Fan&rft.date=2018-05-01&rft.pub=IEEE&rft.eissn=2379-447X&rft.spage=1&rft.epage=5&rft_id=info:doi/10.1109%2FISCAS.2018.8350918&rft.externalDocID=8350918