Gated contact chains for process characterization in FinFET technologies

• Published in: 2014 International Conference on Microelectronic Test Structures (ICMTS) pp. 64 - 69
• Main Authors: Brozek, Tomasz, Lam, Stephen, Shia Yu, Pak, Mike, Liu, Tom, Valishayee, Rakesh, Yokoyama, Nobuharu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2014
• Subjects: Characterization; Contact; Contacts; Failure Mode; FinFET; FinFETs; Junctions; Logic gates; Observability; Resistance; Test Structure
• ISBN: 1479921939; 9781479921935
• ISSN: 1071-9032; 2158-1029
• DOI: 10.1109/ICMTS.2014.6841469

Contact Chain is a well known element of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes examples of test structures for contact process development for FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g. bad transistor with very high threshold voltage) a series of measurement under various test conditions is performed and analysed to extract the contact failure rate. We also demonstrate the application of such structures in FinFET process characterization.