A novel divided STI-based nLDMOSFET for suppressing HCI degradation under high gate bias stress

• Published in: 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) pp. 299 - 302
• Main Authors: Mori, Takahiro, Kubo, Shunji, Ipposhi, Takashi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2018
• Subjects: Buffer layers; Degradation; Electric fields; Human computer interaction; Impact ionization; Logic gates; Stress
• DOI: 10.1109/ISPSD.2018.8393662

Incorporating a P-type REduced SURface Field (RESURF) layer under an N-type drift region in an nLDMOSFET is a well-known means of improving the trade-off between the on-resistance (Rsp) and off-state breakdown voltage (BVoff), as well as reducing hot carrier injection (HCI) degradation. However, the N-type buffer layer under the drain N+ region must be eliminated to maintain a high BVoff in such structures. Generally, HCI degradation occurs near the channelside STI edge at the maximum substrate current (Isubmax). In addition, new HCI degradation occurs in the vicinity of the drain-side STI edge under high gate bias and drain bias conditions because a high electric field is generated near this region. Herein, a new nLDMOSFET in which the STI is divided near the drain-side edge is proposed to suppress this HCI degradation while maintaining the Rsp-Bvoff trade-off.