Study on board level solder joints reliability analysis of the copper stud bump flip-chip

• Published in: 2010 11th International Conference on Electronic Packaging Technology and High Density Packaging pp. 1018 - 1022
• Main Authors: Mu, Wei, Zhou, Dejian, Wu, Zhaohua
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2010
• Subjects: Copper; Fatigue; Finite element methods; Materials; Soldering; Strain; Stress
• ISBN: 9781424481408; 1424481406
• DOI: 10.1109/ICEPT.2010.5582624

In this paper, the investigation focuses on the copper stud bump solder joint thermal-mechanical reliability. The copper stud bump processing is simulated by FEM software Ansys/Ls-dyna, and then the relationship between the copper stud bump and processing parameters (bonding force, ultrasonic power, bonding time and bonding temperature) is studied. Based on the simulation result, the dimension of the bonded copper stud bump is obtained, and then the 3D model of chip with copper stud bump is developed. Only one-fourth model is used to reduce the computer work. The solder alloy, SnPb63/37, is modeled as rate-dependant visco-plastic material using ANAND model. According the JEDEC JESD22-A104, the temperature cycle test is simulated in order to study the distribution of equivalent stress and plastic strain for solder joints array and to located the maximum stress and strain solder joint. Based on modified Manson-Coffin model for life prediction of solder joint, the fatigue life of the key solder joint is predicted. The results show that the dangerous solder joint is located on the corner of the chip, where the max stress and strain is happened.