Graphene devices, interconnect and circuits - challenges and opportunities

• Published in: 2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 69 - 72
• Main Authors: Stan, M.R., Unluer, D., Ghosh, A., Tseng, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Boundary conditions; carbon nanotubes; Circuit simulation; CNT; Digital circuits; Electric variables; FET circuits; GNR; graphene nanoribbons; Integrated circuit interconnections; Lattices; Nanoscale devices; Photonic band gap; Silicon
• ISBN: 1424438276; 9781424438273
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2009.5117687

Graphene has recently emerged as a serious contender for the post silicon era. Graphene nanoribbon (GNR) devices have similar performance characteristics to carbon nanotube (CNT) ones. However, lithographic patterning methods applied to graphene can avoid the degree of chirality control and alignment issues typical of CNTs, and GNR devices and GNR interconnect can in principle be seamlessly obtained by patterning single graphene sheets, thus leading to monolithically device-interconnect structures. Electrically doped GNR devices in series and in parallel can be used for creating complex GNR FET digital circuits. There are also several important challenges facing the graphene ldquobrave new world,rdquo but many of the difficulties hopefully will have tractable solutions. This paper examines the topic of GNR FET circuit design from a bottom-up theoretical perspective, starting with GNR device and interconnect modeling and simulation, while trying to reconcile theory with some recent experimental results.