Multi-Split-Row Threshold decoding implementations for LDPC codes

• Published in: 2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2449 - 2452
• Main Authors: Mohsenin, T., Truong, D., Baas, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Digital video broadcasting; Hardware; Integrated circuit interconnections; Iterative algorithms; Iterative decoding; Message passing; Parity check codes; Partitioning algorithms; Throughput; Wire
• ISBN: 1424438276; 9781424438273
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2009.5118296

The recently introduced Split-Row Threshold algorithm significantly improves the error performance when compared to the non- threshold Split-Row algorithm while requiring a very small increase in hardware complexity. The Multi-Split-Row Threshold decoding algorithm presented in this paper enables further reductions in routing complexity for greater throughput and smaller circuit area implementations. Several Multi-Split-Row Threshold decoder designs have been implemented in 65 nm CMOS and the impact of the different levels of partitioning on error performance, wire interconnect complexity, decoder area, and speed are investigated. The Split-Row-16 Threshold decoder occupies 3.8 mm 2 , runs at 100 MHz, delivers a throughput of 13.8 Gbps at 15 iterations and is only 0.28 dB and 0.22 dB away from SPA and MinSum Normalized.