Generalized Graph Connections for Dataflow Modeling of DSP Applications

• Published in: 2018 IEEE International Workshop on Signal Processing Systems (SiPS) pp. 1 - 6
• Main Authors: Liu, Yanzhou, Barford, Lee, Bhattacharyya, Shuvra S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2018
• Subjects: Adaptation models; Buffer storage; Computational modeling; Data models; Dataflow; Memory management; Signal processing; signal processing systems; Testing
• ISSN: 2374-7390
• DOI: 10.1109/SiPS.2018.8598305

In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes between computations. The buffers are single-input, single-output components that manage data in a first-in, first-out (FIFO) fashion. In this paper, we generalize the concept of dataflow buffers with a concept called "passive blocks". Like dataflow buffers, passive blocks are used to store data during the intervals between its generation by producing actors, and its use by consuming actors. However, passive blocks can have multiple inputs and multiple outputs, and can incorporate operations on and rearrangements of the stored data subject to certain constraints. We define a form of flowgraph representation that is based on replacing dataflow edges with the proposed concept of passive blocks. We present a structured design methodology for utilizing this new form of signal processing flowgraph, and demonstrate its utility in improving memory management efficiency, and execution time performance.