Parasitic characteristics of BGA packages

• Published in: Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) pp. 124 - 129
• Main Authors: Chang, T., Cheng, P.H., Huang, H.C., Lee, R.S., Lo, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: CMOS logic circuits; CMOS technology; Electric variables measurement; Inductance; Low voltage; Packaging; Parasitic capacitance; Power supplies; Semiconductor device measurement; Very large scale integration

With the rapid progress in CMOS VLSI technology, feature size has decreased dramatically from 0.5 to 0.25 /spl mu/m, while chip drivers have become faster with sub-ns transitions. Most modern ICs work with a low power supply voltage with a low logic swing, and have widened their data bus from 16 to...