Estimation of average switching activity in combinational and sequential circuits

• Published in: [1992] Proceedings 29th ACM/IEEE Design Automation Conference pp. 253 - 259
• Main Authors: Ghosh, A., Devadas, S., Keutzer, K., White, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1992
• Subjects: Boolean functions; Circuit simulation; Computational modeling; Delay estimation; Flip-flops; Logic circuits; Power dissipation; Sequential circuits; Switching circuits; Very large scale integration
• ISBN: 9780818628221; 0818628227
• ISSN: 0738-100X
• DOI: 10.1109/DAC.1992.227826

The authors address the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason a general delay model is used in estimating switching activity. The method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. In sequential circuits, the input sequence applied to the combinational portion of the circuit is highly correlated because some of the inputs to the combinational logic are flip-flop outputs representing the state of the circuit. Methods are presented to probabilistically estimate switching activity in sequential circuits. These methods automatically compute the switching rates and correlations between flip-flop outputs.< >