Technology and reliability issues of multilevel interconnects in bipolar, BiCMOS and CMOS VLSIC/ULSICs

It is argued that multilevel metallizations are the key to achieving bipolar, CMOS and BiCMOS VLSI/ULSICs with superior performance and higher packing density. It is also concluded that Al-based multilevel metallizations with SiO/sub 2/ as the interlevel dielectric (ILD) are going to remain the most...

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Published in1993 Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting pp. 12 - 19
Main Authors Saxena, Ramkumar, Ghosh, Bourgeois
Format Conference Proceeding
LanguageEnglish
Published IEEE 1993
Subjects
Aluminum integrated circuit conductors
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Abstract It is argued that multilevel metallizations are the key to achieving bipolar, CMOS and BiCMOS VLSI/ULSICs with superior performance and higher packing density. It is also concluded that Al-based multilevel metallizations with SiO/sub 2/ as the interlevel dielectric (ILD) are going to remain the most widely used VLSI/ULSI technology. The fundamental properties and limitations of multilevel metallizations are summarized, and solutions developed for many of the limitations are noted.
AbstractList It is argued that multilevel metallizations are the key to achieving bipolar, CMOS and BiCMOS VLSI/ULSICs with superior performance and higher packing density. It is also concluded that Al-based multilevel metallizations with SiO/sub 2/ as the interlevel dielectric (ILD) are going to remain the most widely used VLSI/ULSI technology. The fundamental properties and limitations of multilevel metallizations are summarized, and solutions developed for many of the limitations are noted.
Author Ramkumar
Bourgeois
Ghosh
Saxena
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Snippet It is argued that multilevel metallizations are the key to achieving bipolar, CMOS and BiCMOS VLSI/ULSICs with superior performance and higher packing density....
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SubjectTerms Aluminum integrated circuit conductors
Title Technology and reliability issues of multilevel interconnects in bipolar, BiCMOS and CMOS VLSIC/ULSICs
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