Clustering and load balancing for buffered clock tree synthesis

• Published in: Proceedings International Conference on Computer Design VLSI in Computers and Processors pp. 217 - 223
• Main Authors: Mehta, A.D., Yao-Ping Chen, Menezes, N., Wong, D.F., Pilegg, L.T.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 1997
• Subjects: Capacitance; Clocks; Clustering algorithms; Contracts; Delay effects; Frequency; Load management; Load modeling; Tree data structures; Wire
• ISBN: 9780818682063; 081868206X
• ISSN: 1063-6404
• DOI: 10.1109/ICCD.1997.628871

Buffers in clock trees introduce two additional sources of skew: the first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees.