Hardware implementation of SHA-3 candidate based on BLAKE-32

• Published in: 2012 5th International Conference on Biomedical Engineering and Informatics pp. 1317 - 1320
• Main Authors: Zhenglin Liu, Xin Dong, Yizhi Zhao, Dongfang Li
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.10.2012
• Subjects: BLAKE-32; FPGA; hardware implementation; Hash function; SHA-3
• ISBN: 9781467311830; 1467311839
• DOI: 10.1109/BMEI.2012.6512910

Quality of hardware implementation is an important factor in selecting the NIST SHA-3 competition finalists. As a third-round candidate algorithm of SHA-3, BLAKE algorithm achieved excellent performance in software implementation. In order to adapt to the resource-limited and high-speed system, this paper carried out a [4G] hardware architecture based on BLAKE-32 algorithm. To complete the calculation, our architecture divides each round cycle into two cycles and each cycle executes 4G functions. Therefore, by adopting this architecture, the resources consuming can be reduced and a higher working frequency can be achieved. After validating the Verilog implementation of our architecture on a FPGA platform, the simulating results show that our [4G]-BLAKE structure has several advantages as a 26.8% area reducing, an up to 112 MHz acceleration in maximum working frequency and an up to 2048 Mbit/s enhancement in maximum throughput rate.