A unified architecture for DPA-resistant PRESENT

• Published in: 2012 International Conference on Innovations in Information Technology pp. 244 - 248
• Main Authors: Zhao, Wei, Wang, Yi, Li, Renfa
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.03.2012
• Subjects: CMOS integrated circuits; Computer architecture; Encryption; Field programmable gate arrays; Hardware; Service oriented architecture
• ISBN: 9781467311007; 1467311006
• DOI: 10.1109/INNOVATIONS.2012.6207741

Recently, there is a new kinds of cryptographic algorithms are proposed to meet the requirements of "lightweight" applications. PRESENT is one of them, which is built based on 4-bit substitution transformation (S-box) and suitable for low cost hardware implementations. Usually, there needs two 4-bit S-boxes, S p , IS p , for PRESENT encryption and decryption, in which IS p can be computed from S p . Therefore, we proposed a unified architecture to supporting the operations of PRESENT encryption and decryption. There also exists a kind of power analysis attacks pose a serious threat on hardware based PRESENT. In order to resist against DPA, we proposed a new masking scheme for PRESENT, in which the nonlinear substitution needs to be carefully masked. In order to reduce the hardware resources for the proposed masking scheme, we reuse the masked S p to generate masked IS p . The experimental results show that our proposed unified masked PRESENT takes up only one time larger than the unmasked existing design. But, it is obvious that our proposed design has the ability to defend against DPA.