Overlapped decoding for a class of quasi-cyclic LDPC codes

• Published in: IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004 pp. 113 - 117
• Main Authors: Sang-Min Kim, Parhi, K.K.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Applied sciences; Belief propagation; Clocks; Coding, codes; Digital video broadcasting; Error correction codes; Exact sciences and technology; Floors; Information, signal and communications theory; Iterative algorithms; Iterative decoding; Parity check codes; Signal and communications theory; Sum product algorithm; Telecommunications and information theory; Turbo codes; Signal processing; Cyclic code; Parity check codes; Decoding; Implementation
• ISBN: 9780780385047; 0780385047
• DOI: 10.1109/SIPS.2004.1363034

In low-density parity-check (LDPC) code decoding with the iterative sum-product algorithm (SPA), due to the randomness of the parity-check matrix, H, the overlapping of the check node processing unit (CNU) and variable node processing unit (VNU) in the same clock cycle is difficult. The paper demonstrates that overlapped decoding can be exploited as long as the LDPC matrix is composed of identity matrices and their cyclic-shifted matrices, i.e., the parity-check matrix, H, belongs to a class of quasi-cyclic LDPC codes. It is shown that the number of clock cycles required for decoding can be reduced by 50% when overlapped decoding is applied to a (3,6)-regular LDPC code decoder.