A 80 Mb/s low-power scalable turbo codec core

• Published in: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) pp. 389 - 392
• Main Authors: Giulietti, A., Bougard, B., Derudder, V., Dupont, S., Weijers, J.-W., Van der Perre, L.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: 3G mobile communication; Algorithm design and analysis; Applied sciences; Circuit properties; CMOS technology; Decoding; Delay; Design methodology; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Mathematical model; Recording and replay of audio and video signals; Signal convertors; Storage and reproduction of information; Throughput; Turbo codes; Data storage; Data transmission; Turbo code; Flexibility; Implementation; Optimization; Codec; Power consumption; Wide band; Coding; Complementary MOS technology; Low-power electronics; Gain
• ISBN: 9780780372504; 0780372506
• DOI: 10.1109/CICC.2002.1012851

Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this domain, special turbo codec architectures that cope with low latency, high throughput, low power consumption and high flexibility are needed. This paper presents an implementation of a convolutional turbo codec core based on innovative solutions for those requirements. The combination of a systematic data storage and transfer optimization with high and low level architectural solutions yields a final throughput up to 80.7 Mb/s, a decoding latency of 10 /spl mu/s and a power consumption of less than 50 nJ/bit. The 14.7 mm/sup 2/ full-duplex full-parallel core, implemented in a CMOS 0.18 /spl mu/m technology, is a complete flexible solution for broadband turbo coding.