A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

An SSC-compliant 5 Gb/s transceiver in 65 nm CMOS is developed and tested. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase difference between the sampling clock and the signal. The phase tracking of the input signal and the data decision are perf...

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Published in2010 IEEE International Solid-State Circuits Conference - (ISSCC) pp. 168 - 169
Main Authors Yamaguchi, H., Tamura, H., Doi, Y., Tomita, Y., Hamada, T., Kibune, M., Ohmoto, S., Tateishi, K., Tyshchenko, O., Sheikholeslami, A., Higuchi, T., Ogawa, J., Saito, T., Ishida, H., Gotoh, K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2010
Subjects
Adaptive equalizers
Clocks
Finite impulse response filter
Frequency
Logic
Physical layer
Propagation losses
Quantization
Transceivers
Transmitters
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Summary:An SSC-compliant 5 Gb/s transceiver in 65 nm CMOS is developed and tested. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase difference between the sampling clock and the signal. The phase tracking of the input signal and the data decision are performed entirely in the numerical domain.
ISBN:1424460336
9781424460335
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5434001