A SHA-512 Hardware Implementation Based on Block RAM Storage Structure

• Published in: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) pp. 132 - 135
• Main Authors: Yang, Mingyuan, Zhang, Yemeng, Yang, Bohan, Wang, Hanning, Yin, Shouyi, Wei, Shaojun, Liu, Leibo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2022
• Subjects: BRAM; Folding; Hardware; Internet of Things; Random access memory; Reallocation; Reconfigurable logic; Resource management; SHA-512; Table lookup; Throughput
• DOI: 10.1109/IPDPSW55747.2022.00031
• ISBN: 9781665497480

The Secure Hash Algorithms (SHAs) are essential building blocks of modern cryptographic systems. The imple-mentation dimensions of secure hash algorithms are explored for different application scenarios. Cloud servers may favor an implementation with considerable throughput, while a compact implementation with acceptable speed and sustainable power is crucial for the Internet of Things (IoT). In this paper, we present an implementation of SHA-512 for FPGA platform based on Block RAM (BRAM) storage structure. Three implementation techniques are proposed to facilitate the usage of BRAMs as replacements for Look-Up Tables (LUTs) and Flip-Flops (FFs) to achieve a balanced FPGA utilization. Compared to other FPGA implementations of SHA-512, our design has one of the smallest slice consumption while maintaining a moderate but sufficient throughput for cryptographic applications like the post-processing of true random number generators (TRNGs).