Robust hardware-software Co-simulation framework for design and validation of Hybrid Systems

• Published in: 2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) pp. 1 - 11
• Main Authors: Sood, Surinder, Malik, Avinash, Roop, Partha
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13.10.2022
• Subjects: Co-simulation; Hardware; Hybrid Automata (HA); Interconnected systems; Jitter; Measurement; MITL; Real-time systems; Robustness; Software; validation
• DOI: 10.1109/MEMOCODE57689.2022.9954590

Model based design of embedded controllers is prevalent across different industries. The final step in model based design is synthesis of hardware (or software) controller and then testing the synthesized controller in closed-loop with the plant model - this is termed as co-simulation. Standard cosimulation approaches use asynchronous communication fabric. However, they are known to suffer from race conditions, jitter, etc, making real-time property validation difficult. Current approaches to co-simulation problems either require complex middle-ware or require synthesis of the controller and plant for synchronous execution. However, these approaches are unsuited for hybrid system control design and validation, as they require the plant model to execute at an arbitrarily small simulation step, while the synthesized controller executes at its own rate if any. The small simulation step slows down the simulation and such a setup does not guarantee level crossing detection. In this paper, we propose a novel Metric Interval Temporal Logic (MITL) based validation and Hardware in Loop (HIL) co-simulation framework, which synchronizes and integrates the controller synthesized in hardware and the plant executing in software. A discrete controller handles a level crossing generated by the plant, which evolves on variable step size. The traces generated from the closed-loop operation of the overall system are used to validate MITL properties. Finally, the controller hardware and the plant model are adjoined via a communication architecture, whose sample time is dependent upon the robustness estimates of the MITL properties, which is necessary to guarantee validation correctness.