High Throughput High Performance NoC Switch

Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while pr...

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Bibliographic Details
Published in2008 NORCHIP pp. 237 - 240
Main Authors El ghany, Mohamed A. Abd, El-Moursy, Magdy A., Ismail, Mohamed
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2008
Subjects
BFT
Delay
Electronic mail
Frequency
Graphics
Integrated circuit interconnections
Latency
Multiprocessor interconnection networks
Network-on-a-chip
NoC
Switches
Throughput
Tree graphs
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Summary:Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch.
ISBN:1424424925
9781424424924
DOI:10.1109/NORCHP.2008.4738319