A 0.16mm2 12b 30MS/s 0.18μm CMOS SAR ADC based on low-power composite switching

This work proposes a 12b 30MS/s 0.18μm SAR ADC based on a low-power composite switching technique to reduce the required number of capacitors and switching energy. The proposed composite switching employs VCM-based switching and monotonic switching sequences while minimizing the switching power cons...

Full description

Saved in:
Bibliographic Details
Published in2015 International SoC Design Conference (ISOCC) pp. 77 - 78
Main Authors Jong-Min Jeong, Tai-Ji An, Hee-Wook Shin, Gi-Wook Lee, Seung-Hoon Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2015
Subjects
analog-to-digital converter (ADC)
C-R hybrid digital-to-analog converter (DAC)
Capacitors
CMOS integrated circuits
composite switching
image sensor
Power demand
split capacitor
Switches
Switching circuits
System-on-chip
Topology
Online AccessGet full text

Cover

More Information
Summary:This work proposes a 12b 30MS/s 0.18μm SAR ADC based on a low-power composite switching technique to reduce the required number of capacitors and switching energy. The proposed composite switching employs VCM-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. A split capacitor topology implements the VCM-based switching scheme effectively without extra switches in the DAC and the SAR logic. Moreover, the proposed C-R hybrid DAC architecture minimizes the DAC area by reducing the total number of unit capacitors in the DAC up to 32. The prototype ADC in a 0.18μm CMOS technology occupies an active die area of 0.16mm 2 and consumes 1.93mW at a 1.8 V supply voltage without on-chip I/V references.
DOI:10.1109/ISOCC.2015.7401641